Bus and interface system for consumer digital equipment

ABSTRACT

A system for generating a signal for coupling digital audio, video and data signals in compressed form via a bus. A processing means formats the digital audio, video and data signals into superpackets for transmission via the bus. Each superpacket comprises a timestamp, and a transport packet, representative of the digital audio, video and data signals. The superpackets have a fixed duration and occur at variable intervals. Devices receive the superpacket signal and may utilize the timestamps for clock synchronization. A recording and replay device processes the variable superpacket signal occurrence for recording. Reproduced timestamps are utilized to control restoration of the superpacket signal to have substantially the duration and occurrence as when formatted for bus transmission. A simplified bus couples superpackets between devices. An indicia is added to a superpacket signal to provide automatic control of device bus interfaces. The automated interface control is also responsive to device control status.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation in part of application Ser. No.08/292,908 filed Aug. 19, 1994, now U.S. Pat. No. 5,568,403 andPCT/US96/07581 filed May 23, 1996.

This invention relates to a bus interface system/apparatus for couplingaudio, video and data processing systems, and in particular to couplingdigital signals for digital recording and reproduction.

BACKGROUND OF THE INVENTION

It is known in the audio/video electronics arts to interconnect avariety of consumer electronic processing devices on a bus structure, sothat signal available at one device may be utilized by another deviceconnected on the bus. For example audio/video signal available from atelevision receiver may be applied to a video cassette recorder forstorage, or the audio from a television receiver may be applied to acomponent stereo system for reproduction etc. Examples of this type ofaudio/video interconnect systems may be found in U.S. Pat. Nos.4,575,759; 4,581,664; 4,647,973; and 4,581,645.

The signals distributed in these analog bus systems are relatively selfcontained. That is they include all the timing information necessary forthe respective devices connected to the bus to decode the respectivesignals.

Currently there are a number of compressed audio and video transmissionsystems, such as the Grand Alliance HDTV system proposed for terrestrialhigh definition television broadcasting, or the DirecTV™ system whichcurrently broadcasts compressed NTSC signal via satellite. Both systemstransmit program material in transport packets, and transport packetsfor different programs and/or program components may be time divisionmultiplexed in a common frequency band. Respective packets undergo noisedetection/correction encoding prior to transmission and after reception,and the transport packets are thereafter reconstituted in a receiver.Recording apparatus (e.g. VCR or video disc) and authoring apparatus(e.g. cameras or camcorders) for compressed signals, on the other hand,may process the compressed signals in the same packet format, howeverthey may not require the same noise processing. As a consequence theconveyance of signal between processing components is most convenientlyeffected in packet form.

Problems arise in communicating compressed signals between processingcomponents if the packetized format is subjected to timing variations orperturbations. Such timing variations may result when one of theprocessing components is a recording device. A first problem resultsfrom the fact that synchronization indicia is not included in alltransport packets of compressed data. A further problem results from thenon-uniform generation or delivery rate of transport packets which isnot suited to recording directly. In addition, a digital recordingsystem may benefit from a continuous signal presence in order tosimplify data clock recovery techniques. Furthermore, to facilitate thereproduction of compressed data suitable for decoding may require asuitable timing reference be included during recording, and a relativelyprecise timing reference for use during reproduction. A recorded timingindicia may facilitate the elimination of data timing perturbations anddiscontinuities resulting from record/replay processing and enable therecorded signal timing to be restored to that existing prior torecording.

SUMMARY OF THE INVENTION

A signal processing apparatus for processing a data stream comprising apacketized signal subjected to timing perturbations. The packetizedsignal comprises a plurality of superpackets and each of thesuperpackets has a transport packet and a timestamp, the timestamps areindicative of gaps between corresponding parts of superpackets prior tothe timing perturbation. The apparatus comprises a means for receivingthe superpackets from the packetized signal subject timing perturbation.A storing means is coupled to the receiving means for storing thesuperpackets. Timestamps from each of the received superpackets are readby a reading means. A counter and the reading means are coupled to ameans for generating a control signal. The control signal indicates eachsuccessive coincidence between the timestamps from the receivedsuperpackets and a count of the counter. The control signal initiatesreading of the superpackets from the storing means.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the following drawingswherein;

FIG. 1 is a block diagram of an inventive embodiment of a daisy chainconnection of bus hardware including a number of bus/device interfaces;and

FIG. 2 is a block diagram of a portion of one of the bus interfaces ofFIG. 1; and

FIG. 3 is a first system block diagram illustrating a receiver coupledvia a data bus to a source of timing perturbation and an inventivesuperpacket restoration block.

FIG. 4A is a waveform and pictorial representation of bus superpacketsaccording to a first arrangement, and FIG. 4B illustrates an alternativesuperpacket arrangement; and

FIG. 5 is a system block diagram including a receiver coupled to adigital recording and replay device and employing various inventiveembodiments;

FIGS. 6 and 7 are block diagrams of apparatus for forming a superpacket;and

FIG. 8 is a further system block diagram including a digital recordingand replay device and employing various inventive embodiments.

FIG. 9 is a circuit diagram of an inventive controller advantageouslyused in FIGS. 8 and 10.

FIG. 10 is another system block diagram including a digital recordingand replay device and employing various inventive embodiments.

DETAILED DESCRIPTION

Referring to FIG. 1, there is shown a cascade of audio-video-data AVDbus interfaces interconnected by an AVD bus. Each interface isbidirectional in that it can be conditioned to provide signal to, oraccept signal from a device component. However, it cannot do bothconcurrently, and will be conditioned to do one or the other for asession. Each interface includes an output buffer, OB, for driving acomponent device with signal provided by the bus. Each interfaceincludes an input buffer, IB, for driving the bus with signal providedfrom the device component. Both the input and the output buffers areselectably coupled to the bus via switches which are controlled by amaster controller. Thus the direction of applying signal to, orreceiving signal from the bus may be determined with a high degree offlexibility.

Each interface may include a half duplex transceiver, at bothconnections to the AVD bus, for coupling signal from the bus to theinterface. The bus includes a pair of control lines on which serialcontrol signals are communicated from a master controller. The controlsignals may include addresses so that respective ones of the interfacesmay be selectively controlled.

An exemplary interface switch apparatus is illustrated in FIG. 2. Inthis illustration, the AVD bus is presumed to consist of three linepairs or six conductors. All of the line pairs carry bit-serial signals.Two of the conductors, (the control pair) are consigned to carry thecontrol signals. Each decoder carries a unique address which enablesindividual commands to be delivered to specific interfaces. Responsiveto a control signal directed to the specific interface, the decoderoutputs steering signals to the respective demultiplexers 01, 02, 03 and04. The control signals determine: which of the respective busconductors are coupled to the output port OUT, which are in turn coupledto the output buffer OB; and which of the respective bus conductors arecoupled to the input port IN, which are in turn coupled to the inputbuffer IB; and which of the conductors will transit the interfacebetween right and left input/output ports. The use of demultiplexersallows the daisy chain connection between components to be broken,permitting independent communications between components on either sideof the break while employing the same conductors. Consequently a greaternumber of unique communications may be performed with fewer conductorsin the bus structure.

FIG. 3A illustrates a first exemplary system employing an integratedreceiver decoder or IRD 100 which is coupled via the advantageousinterface switch apparatus 101, as illustrated in FIGS. 1 and 2, to theAVD bus 500. A television receiver display 110 is coupled to IRD 100 andreceives either R.F. or base band video signals for display. The AVD bus500 couples control signal data and two streams of signal format data.

In FIG. 3A it is assumed that the signal to be communicated is providedin the form of transport packets such as defined in the system layer ofthe MPEG2 video standard, or the transport layer of the Grand Alliancesignal format. In both the MPEG2 video standard and the transport layerof the Grand Alliance signal format, transport packets are associatedwith timestamps or PCRs which allow re-synchronization of local systemclocks to the original encoder clock frequency. Hence, havingsynchronized the local system clock generator, the transport packets maybe processed to remove jitter or timing perturbations which mayaccumulate, for example, during transmission by switched bus structuresand processing etc. However, transport packets may be subjected tojitter and timing discontinuities which may not be correctable based onthe variable, and specified intermittent occurrence of timestamps in thetransport stream. The AVD bus 500 is illustrated coupled to a source oftiming perturbation, block 05 which may impart a timing error Δt to thedata streams present on the bus. The source of timing perturbations orjitter may result from bus switching, bus arbitration, timebasemodulation, or recording and reproduction processes. AVD bus 500 withtiming error Δt, is coupled to block 50 which removes the timing errorcomponent, and restores the bus signal components.

To facilitate the removal of the timing error Δt from the AVD signals,IRD 100 processes transport packets to form a further packet, designatedherein as a superpacket, prior to transmission via AVD bus 500. Eachsuperpacket includes a timestamp, the transport packet and a reserveddata area which may include a playback rate code. Two timestampembodiments are shown in FIGS. 4A and 4B. The timestamp is a timing codewhich is a sample of an oscillator count taken at a specific instant,for example, at the occurrence of a frame clock pulse. Since a timestampis added to each superpacket, the timestamp may be utilized tofacilitate correction of timing jitter and perturbations impressed onthe corresponding superpacket and its contents. The playback rate codemay be used by a recording device to determine the rate at which aparticular signal is to be recorded or played back. The playback rate iscoded relative to the recording rate and is read and utilized by anyrecording devices connected to the AVD bus. The purpose of the playbackrate code is to allow recording at a relatively high bit rate andplayback at a normal bit rate.

FIG. 3A depicts an integrated receiver decoder IRD 100 which receives aradio frequency signal from, for example, antenna 10 or a cable source,not shown. The RF signal is tuned by tuner 11 to receive and demodulatea user selected program. The tuner output packet stream is coupled toblock 12, packet source, which separates the user's specific programtransport stream TP from other program streams present in the receivedpacket stream. The transport stream is coupled to a demultiplexer 13where a program clock reference PCR value is extracted from thetransport stream responsive to control by a demultiplexer controller 14.The demultiplexer controller 14 is controlled to extract the PCR by apacket timing pulse P which is coincident with and indicates theoccurrence of respective transport packets. Packet timing pulse P isderived from the program transport stream by packet source 12. The PCRvalue, which is demultiplexed by block 13, is coupled for storage bylatch 15.

A voltage controlled crystal oscillator 17 operates at a nominal clockfrequency of 27 MHz and is controlled by a clock controller 16. Acontrol signal E is generated responsive to a difference between thereceived PCR value, stored in latch 15, and a latched value derived bycounting VCXO 17 in counter 18 and storing in latch 19. Thus VCXO 17 issynchronized by the received PCR value, which in turn is representativeof the clock frequency at the time of encoding. Let the successivetimestamp values be designated TS_(n) and TS_(n+1). Let correspondingsuccessive count values stored in the latch 19 be designated LCR_(n) andLCR_(n+1). The clock controller 16 reads the successive values of TS'sand LCR's and forms an error signal E proportional to the differences

E=>|TS_(n)−TS_(n+1)|−|LCR_(n)−LCR_(n+1)|

The error signal E, is applied as a control signal to condition thevoltage controlled oscillator 17 to produce a frequency equal to thefrequency of the system clock from which the PCRs were encoded. Theerror signal E produced by the clock controller 16 may be in the form ofa pulse width modulated signal, which may be rendered into an analogerror signal by low pass filtering, not shown. The constraints on thissystem are that the counters throughout the system, namely encoder,decoder and recorder, count the same frequency or even multiplesthereof. This requires that the nominal frequency of the voltagecontrolled oscillator be fairly close to the frequency of the systemclock in the encoder.

It will be noted that the occurrence of transport packets generated asillustrated for example, in FIGS. 3, 5, 6 and 7 are synchronous with asystem clock. The system clock was in turn synchronized to an encoderclock via PCR's located within the transport stream and derived inpacket source 12. The occurrence of these transport packets are timestamped in cooperation with the receiver synchronous clock, and therespective transport packets are tagged with timestamps, derived fromthe clock before application to the AVD bus.

The operation of superpacket generator 98 is as follows. A timestamp TSis formed in latch 20 which captures a counter value produced bycounting pulses from an oscillator, for example VCXO 17 in counter 18.The latched counter value is representative of the frequency of theoscillator at a specific instant, for example, an edge of a frame clocksignal FC, or the start of a transport packet. Timestamp TS is coupledto block 22 where it is combined with control data, for example playbackspeed data PB from controller 23, and a delayed transport packet TP fromdelay 21. The formatted superpacket SP is coupled from formatting block22, of generator 98, for transmission via AVD bus 500 responsive tocontrol by controller 23.

FIG. 4A is a pictorial representation of a superpacket signal asconveyed by AVD bus 500. A frame clock is provided on one of the busconductors and may be used to indicate the occurrence or presence of asuperpacket on another of the AVD bus conductors. When frame clock FC isin a high state, a superpacket is framed within and coincident with thehigh state. The high state or active interval of the frame clock is ofconstant duration for all packets, and in this example is equal to theduration of 191 eight bit bytes. These 191 bytes are divided between a20-bit timestamp, a 4-bit playback rate code and a 188-byte transportpacket. If a transport packet is less than 188-bytes it is loaded in theleading part of the transport packet portion of the superpacket. FIG. 4Aillustrates a first sequence where the first 20 bits of data representthe timestamp, the second 4 bits represent the playback rate code andthe final 188-bytes comprise the transport packet. FIG. 4B illustrates asecond superpacket arrangement where the first sequence comprises 12bits of reserved data, for example playback rate code, the second 20bits represent the timestamp. The final portion of the superpacketcomprises the transport packet. The superpacket stream occurs in burstswith intervening gaps, where the bursts comprises the superpacket andtransport packet etc., which may, for example, contain 140 or 188 bytes,representing DSS™ and MPEG packets respectively. The active portions ofthe frame clock are of constant duration, with inactive intervals ofvariable duration which correspond with gaps resulting from deleted ornon-selected elemental streams. These variable periods of inactivity mayprovide considerable flexibility in the formation of superpackets.

Timestamps are samples of counts from a high frequency oscillator whichis assumed to run stably, without perturbation. Hence timestamp values,or oscillator counts, may be communicated, for example, to provideoscillator synchronization or to uniquely identify the occurrence of aspecific instant or event. Differences between timestamps valuesrepresent an elapsed number of oscillator cycles, which mayalternatively be considered to represent an elapsed time intervalbetween timestamps. However, if the elapsed time interval betweentimestamps is disturbed or perturbed, i.e. the occurrence, or spacingbetween timestamps is not the same as when encoded or time stamped, thetimestamp values can not be used to control or synchronize a “receiving”node oscillator.

FIG. 3B illustrates in simplified form, processing employed withinsuperpacket restoration block 50 which utilizes superpacket timestampvalues to remove timing error Δt impressed, for example, on signalscoupled from AVD bus 500. The operation of superpacket restoration block50 is as follows. The AVD bus 500 is received by interface switchapparatus 102 which is enabled by a control signal on control conductorsof bus 500. The superpacket signal with time perturbations SP±Δt, iscoupled from the data bus to a demultiplexer DEMUX 52 which reads thetimestamp from the superpacket. The superpacket signal is also coupledto a buffer store STORE S. PACK 51, which is controlled to store thesuperpacket responsive to, for example, a frame clock signal FC, orother control signal derived from the control conductors of AVD bus 500.An oscillator 54 has a stable free running frequency and has an outputsignal CK which is coupled to buffer store 51 and to counter 53.Oscillator 54 is required to have a nominal frequency which is fairlyclose to the frequency of the clock employed in formatting thetimestamp. The count value CTR, of counter 53 and the demultiplexedtimestamp TS, are coupled to a buffer store read controller READ CTRL55. The read controller compares the separated timestamp value with thefree running oscillator count, and at coincidence generates a read, oroutput control signal EN. The output control signal EN is coupled tobuffer store 51 which outputs the respective superpacket responsive tothe control signal. In addition to re-establishing superpacket starttime, the superpacket bit rate is restored by clock signals CK derivedfrom oscillator 54. Thus, by means of the superpacket timestamp and thestable, free running oscillator, the timing error Δt is removed and eachsuperpacket SP is restored to occur at substantially the same time aswhen formatted by generator 98 of IRD 100. Since the superpacket isclocked out by a clock signal from oscillator 54, the superpacket hassubstantially the same bit rate as when formatted. Furthermore, sincethe superpacket occurrence and duration are restored to nominally thevalues existing at the time of formatting, so too are the variablelength, intervening gaps. The restored superpacket SP may be returned toAVD bus 500 for re-transmission to other bus interface switches beyondthe source of timing perturbation, or superpacket SP may be utilizedwithin an apparatus of which superpacket restoration block 50 may formpart.

In general, recording systems rely on signal presence or absence toprovide an elementary level of signal loss detection. Additionally,continuous signal presence, particularly in a digital recording systemis advantageous for data clock recovery. Since magnetic recordingsystems are subject to random signal losses of variable, andunpredictable duration, it is beneficial to employ a record signalhaving a constant bit or clock rate. Thus with such a recorded signal,periods of missing data may be considered representative of recordingmedia losses.

In FIG. 5 bus interface 102 accepts bursts of superpackets from bus 500.The superpackets are coupled to signal sorter 202 which containsdemultiplexer 30 for separating or reading the constituent parts of thesuperpacket. In the exemplary system of FIG. 5, superpackets SP, ratherthan transport packets are recorded on recording media 405. Thesuperpackets, with variable length gaps, are coupled to a data buffer281 which forms part of recording circuitry 28. Data buffer 281 andassociated circuitry may be clocked with signals derived from a syncgenerator 99. Sync generator 99 may be synchronized by clock signalsgenerated by a stable, VCXO clock generator 37. Clock generator 37 maybe synchronized to the superpacket timestamp during a record mode. Databuffer 281 smoothes the bursts of superpackets to remove orsubstantially reduce the intervening variable duration gaps for furtherprocessing within recording circuitry 28. For example, Reed Solomonerror detection and correction codes may be computed and added to thebuffered superpackets as illustrated in block 282. The bufferedsuperpacket data may be stored as depicted by Format Sync Block 283. Itis known to shuffle or interleave data prior to recording to mitigateeffects of media damage which may result in uncorrectable errors duringreproduction. The shuffling or interleaving may be carried out over theperiod of a recorded segment, i.e. a head scan, or an average pictureinterval. In addition to shuffling, the data may formatted by FormatSync Block 283, to produce sync blocks having a data structure which maycomprise a preamble or sync word identifying the start of the track, anidentification code, the data to be recorded (superpacket) and apostamble.

Error coded, shuffled and syncblock formatted data may be furtherprocessed for record coding, in an embodiment illustrated as recordblock REC. CODE 284. Record coding may be used to reduce or eliminateany DC components in the data stream, and may also be used to tailor therecorded frequency spectrum of the processed superpacket signal.

The replay process performs the inverse of the record mode signalprocessing. The replay signal 407 from transducer 406 is code convertedin block REC. DECODE 271, to restore the error coded, shuffled formatteddata signal. The start of the data track is identified by the sync wordand the data is clocked into a memory, represented by DEFORMAT SYNCBLOCK 272, to enable deformatting of the recorded shuffled structure.The memory of block 272 is read out in a manner complementary to thatemployed for shuffling prior to recording. Thus by shuffling anddeshuffling, media derived errors are dispersed throughout the datacontained in the recorded sector or track. Following deshuffling thedata is error corrected in block 273 using the exemplary Reed Solomoncode added during record processing. Thus output data stream 401, fromreplay circuitry 27, represents the buffered superpacket stream asgenerated by packet buffer 281. However, to enable subsequent decodingby decoder 24 of IRD 100, the buffered superpackets are restored, inblock 453, to more closely represent the timing and intermittent orburst like delivery of the superpackets as formatted by IRD 100 prior torecording. Operation of superpacket restoration circuitry 450 is similarto that described for FIG. 3B and is described following the explanationof oscillator and timestamp synchronization.

FIG. 5 illustrates an exemplary utilization of timestamps forsynchronization and timing purposes in digital recorder 400. In a recordmode, superpackets from one conductor of AVD bus 500 are coupled viainterface switch 102 to signal sorter 202. The frame clock signal FCpresent on another AVD bus conductor is applied to a second input ofsorter 202. An edge detector, 31, detects the transition of the frameclock signal FC which defines the start of the active frame clockinterval, and responsive to such detection, captures in a latch 35 thecount exhibited by a counter 36. Counter 36 counts pulses from a voltagecontrolled oscillator 37 which has a nominal free running frequencyclose to the frequency used to generate the superpacket timestamps.

Simultaneously with capturing the count value in latch 35, the edgedetector 31 alerts demultiplexer controller 33 to provide a sequence ofcontrol signals for controlling demultiplexer DEMUX 30 to separate thecomponents of the superpacket. The timestamp contained in thesuperpacket is separated and stored in a memory 32, for access by aclock controller 39. Depending upon the form of signal the recorder isarranged to handle, DEMUX 30 may be designed to provide the signal in avariety of formats. That is, it may provide the superpacket in toto, asillustrated in FIGS. 4A, 4B, for buffering and recording as shown inFIG. 5. Alternatively DEMUX 30 may be arranged to provide the playbackrate code PB on one port which is accessed by the recorder controlcircuitry 29. Transport packets may be provided at another port as analternative signal for coupling to record buffer circuitry 281.

The clock controller includes apparatus for storing successive valueslatched in latch 35 and successive timestamp values stored in MEMORY 32.The clock controller 39 reads the successive values of timestamps andlatched counter values and forms an error signal E proportional to thedifference. The error signal E, is applied as a control signal tocondition the voltage controlled oscillator 37 to produce a frequencyequal to the frequency of the system clock with which the timestampswere generated. The error signal E produced by the clock controller 39may be in the form of a pulse width modulated signal, which may berendered into an analog error signal by implementing a low pass filter38 with analog components. The constraints on this system are that thecounters at throughout the system, namely encoder, decoder and recorder,count the same frequency or even multiples thereof. This requires thatthe nominal frequency of the voltage controlled oscillator be fairlyclose to the frequency of the system clock in the encoder.

It will be noted that the occurrence of transport packets generated asillustrated in FIGS. 3, 5 and 6, for example, are synchronous with asystem clock. The system clock was in turn synchronized with to anencoder clock via PCR's located within the transport stream and derivedin packet source 12. The occurrence of these transport packets are timestamped in cooperation with the receiver synchronous clock, and therespective transport packets are tagged with timestamps beforeapplication to the AVD bus. At the recorder interface to the AVD bus,the recorder may record the superpacket and may utilize the timestampsto generate a recorder system clock which is synchronous with thetransport packet and the receiver system clock. However, superpackettimestamps may be derived from a stable oscillator, independent of thereceiver system clock, which may also be utilized for recordersynchronization.

Timestamps are samples of counts from a clock oscillator which isassumed to run stably, without perturbation. Hence timestamp values, oroscillator samples, may be communicated for remote synchronization or touniquely identify the occurrence of a specific instant or event.Differences between timestamp values represent an elapsed number ofoscillator cycles, which may be considered to represent an elapsed timeinterval. When digital recorder 400 replays a recorded signal from media405, VCXO 37 may not be controlled in response to reproduced timestamps.Control of oscillator 37 is not possible because, although timestampsrepresent numeric values sampled from a stable oscillator, the elapsedtime intervals represented by timestamp values is violated if thereproduced occurrence a superpackets, or the spacing betweencorresponding points on adjacent superpackets is not the same as whenencoded. Such reproduced timing differences may, for example, resultfrom recorder input buffering, data smoothing, reproducing mechanisminstabilities, and transducer switching.

Hence when digital recorder 400 replays, oscillator VCXO 37 free runs,driving sync generator 99 which provides reference signals for therecorder mechanism and the processes of block 27. The stability of VCXO37 and sync generator 99 is sufficient to facilitate recovery of thebuffered superpackets which are output as signal 401. However,specifications for a “reference” MPEG decoder require that each packetarrive within 25 micro seconds of it's original timing. Thus decoder 24of IRD 100, may require that superpacket signal 401 be restored to moreclosely represent the timing and superpacket occurrence, and thereforetransport packet timing, as when formatted by generator 98 of IRD 100.In addition, although MPEG decoder specifications may specify timingjitter tolerances, a recording and replay signal process may introducetiming perturbations beyond the clock synchronization and buffercapacity of a decoder.

Superpacket signal 401, SP±Δt, may be advantageously restored orreformatted by utilizing the timestamps added to each superpacket.Signal 401 is coupled to demultiplexer 452 where the timestamps areextracted or copied and coupled to demultiplexer control block 451.Timestamps may be demultiplexed by, for example, counting data bitsbased on the superpacket structures illustrated in FIGS. 4A and 4B, andknowing where the start of replay data occurs based on the format of therecorded syncblock and associated sync word. Alternatively, duringsuperpacket buffering, shown in block 28, a timestamp identifier may beadded to provide identification during reproduction. The demultiplexercontrol compares the replayed timestamp value with a continuouslychanging count value produced by counting a free running oscillator, forexample, oscillator 37 and counter 36. Clearly to enable superpackettiming restoration, oscillators of nominally the same frequency arerequired at each end of the system. When the value of counter 36, andthe demultiplexed timestamp are equal, demux control 451 generatessignal EN which initiates the start time of the replayed superpacket.Thus the encoded reference time, for example the start of the transportpacket within the superpacket is restored. Thus each superpacket isrestored to occur at the same oscillator count as when formatted byblock 22. In addition to re-establishing superpacket timing, the bitrate of the superpacket must also be restored. To enable superpacketrestoration, block 453 may comprise a storage buffer coupled to receivereplayed signal 401. Buffer block 453 may be clocked by pulses CK fromoscillator 37, hence each buffered superpacket is read out at a ratedetermined by oscillator 37, which has substantially the same frequencyas used when formatting. Since the superpackets have been retimed tooccur at substantially the original “encoded” time, and the superpacketbit rate is substantially the same as when formatted, thus the variable,intervening gaps between superpackets are also restored. Thus thereproduced signal from restoration block 453 is substantially asformatted and free of recorder derived timing discontinuities andperturbations. The restored superpacket signal 402 is coupled to AVD bus500 via switch 102 which is controlled via control data pair of the bus.

Referring to FIG. 6, a further method of generating superpackets isillustrated and will be described. In this example a camera 40 generatesa video signal. This video signal is compressed in an MPEG encoder 41,and packaged in transport packets by the transport processor 42. TheMPEG encoder 41 in cooperation with a system clock 45 and a modulo Mcounter 43, includes presentation timestamps in the compressed videosignal. The transport processor 42, also in cooperation with the moduloM counter 43, includes program clock references in ones of the transportpackets. The transport processor provides bit-serial transport packetsof the video signal on one output port, and in parallel therewithprovides a timing signal indicative of the start of successive outputtransport packets.

Successive transport packets are delayed in a compensating delay element50, and then applied to a superpacket formatter 47. At the start of eachnew transport packet the count exhibited in the modulo M counter 43 iscaptured in a latch 44, the output of which is coupled to formatter 47.In addition a playback rate control code, PB, is applied from a systemcontroller 46 to the superpacket formatter. In this example it ispresumed that the camera is operating at real time and at normal speed,hence the playback rate code will reflect a playback speed equivalent torecording speed. However, the camera may operate at a higher than normalimaging rate, for example, 90 images per second. Such high rate imagesignals may be used to portray image movement in slow or variablemotion, hence the desired viewing speed may be communicated by theplayback rate control code. For example a playback rate of ⅓ willportray image motion at one third speed. The speed of camera action iscontrolled by a user input 48, which may define a number of variablecoding and compression parameters.

When the timing signal provided by the transport processor indicates theoccurrence of a new transport packet, controller 46 conditions theformatter to first output, in serial form, the reserved data block, forexample 12 bits as illustrated in FIG. 4B, which includes the playbackrate code. Following the reserved data block, the count from latch 44 isoutput in serial form to generate the timestamp. Finally the delayedtransport packet from delay 50 is output in serial form to completesuperpacket formatting. The delay incurred by the transport packet inthe delay element 50 is equivalent to the time necessary to read out thetimestamp and the playback rate code.

The superpackets are applied to a desired one of the conductors in theinterface 49 under control of control signals present on the controlpair of conductors of the interface. In addition controller 46 generatesa frame clock signal FC which is coincident with the superpacket andwhich is applied to a second conductor of the AVD bus at interface 49.If controller 46 is the overall system controller, it will generatecontrol signals which are applied to the control pair. User control 48may provide signal selection and direction. If controller 46 is not thesystem controller, the only interaction with the interface will begeneration of the frame clock in this example.

FIG. 7 illustrates a further example of a superpacket generator. In FIG.7 elements designated with the same numbers as elements in FIG. 6 aresimilar and perform the same function. Transmitted transport packets arereceived by a modem and error corrected by a Reed Solomon decoder of thepacket source 51. The packet source generates outputs pulses P, whichare coincident with and indicate the occurrence of respective transportpackets. The pulses P and the transport packets are applied to aninverse transport processor 53. In this example it is assumed that thesignal applied to the packet source contains time division multiplexedpackets pertaining to different programs and different programcomponents. Respective packets contain program identifiers, PID's, bywhich they are associated with respective programs or programcomponents. The transport processor is conditioned to select onlypackets associated with a desired program. The payloads of these packetsare applied via a direct memory access, DMA, to a buffer memory 54.Respective program component payloads are applied to specific areas ofthe buffer memory. As respective program component processors 55, 56, 57and 58 require component signal data, they request same from theprocessor 53, which reads the appropriate payload via the DMA structure.

Ones of the transport packets contain program clock references, PCR's,which precisely relate the creation of the transport packet to theencoder system clock at generation. The transport processor 53 extractsthese PCR's and applies them to a system clock generator 52. Using thePCR's, clock generator 52 generates a system clock which is frequencylocked to the encoder system clock. The system clock is utilized by theinverse transport processor 53 and the packet source 51, hence thetransport packets are relatively synchronized with their originalcreation timing.

The system clock is counted by modulo M counter 43, and the count valueexhibited by the counter when a pulse P occurs, i.e. when the start of anew transport packet is output by the packet source, is captured bylatch 44 responsive to pulse P. The count from counter 43 is latchedlatch 44 responsive to a packet timing pulse P derived from the receivedtransport stream to be formatted for coupling to the AVD bus. Thislatched count value is utilized as a timestamp. In addition, theassociated transport packet is applied to a compensating delay element50. The delayed transport packet from element 50, the counter value ortimestamp from latch 44, and a playback rate code from a controller 460are applied to respective input ports of a superpacket formatter 47.

The controller 460, under user control 48, communicates with the inversetransport processor to designate which program transport packets are tobe packaged in superpackets. On the occurrence of respective transportpackets, the inverse transport processor provides a pulse to thecontroller 460 whenever a received packet is a desired transport packet.Responsive to this pulse the controller 460 conditions the formatter toform the superpacket with the current timestamp, PB and transportpacket. Note in this example the delay element 50 must accommodate notonly the formation time of the first two data elements of thesuperpacket but also the time required of the inverse processor toascertain that a packet is the one which is desired.

In the foregoing examples the timestamp is generated at the occurrenceof a transport packet. Alternatively timestamps may be generatedrelative to the timing or generation of the superpacket. That is, thetimestamp may define the instant a superpacket is to be output, or theinstant assembly of the superpacket begins. In these instances the timestamp will generally be related to the leading edge of the Frame Clock,though it may not define the timing of this transition. However,whatever timed occurrence the timestamp value represents, the timestampis specific to a particular superpacket and the transport conveyedwithin.

The frame clock FC is not a fixed frequency signal. That is, theinactive portion of the frame clock has a specified minimum and maximumduration. It is specifically desired that the frame clock not be a fixedfrequency clock so that superpackets may be formed at any time atransport packet is available. It is undesirable to use a fixedfrequency frame clock, since this may force a delay in the formation ofa superpacket for transport packets that occurred after the beginning ofan active portion of the frame clock until the subsequent cycle of theframe clock. If the timestamp is to be related to the formation ofsuperpackets or the frame clock, then latches 44 in FIGS. 6 and 7 may beconditioned to capture count values by either the formatters 47 or thecontrollers 46 or 460 respectively.

A second exemplary audio-video-data AVD bus system is illustrated inFIG. 8. This second exemplary AVD system employs a simplified daisychained bus 501 for coupling between an IRD 100, digital recorder 400and a display 110. This simplified bus has only two conductor pairs A/Bwith switch control logic C incorporated at each interface switch matrix101/102. The switch control logic C monitors the state of each pair ofbus 501 and in response to user selected status, for example, playbackor record modes, automatically determines an appropriate signal routingvia bus 501. In simple terms, the switch control logic ensures thatsources of signals are only coupled to signal destinations and that onlyone signal source at a time is coupled to a bus pair. The presence of adata signal on a bus pair is indicated by an indicia Vs. Indicia Vs maybe generated, as shown in exemplary FIG. 9, by element 405 and detectedby element 401.

FIG. 9 illustrates a data bus transmitter and receiver employing aninventive bus status indicator and detector. Ones of the inventivetransmitter circuit are coupled to each input of the interface switch.Ones of the inventive receiver/detector circuitry are coupled to eachbus line coupled to the interface switch. The theory and operation ofbalanced line driving and reception techniques is well known. Theinventive data indicia transmitter 405 and detector 401 utilize thebalanced transmission condition to introduce a DC voltage data indiciaVs, equally into each conductor of the bus pair when coupled to transmitdata. At a receiving bus node the presence of the data indicia Vs isdetected by receiver 401, which forms part of switch control logic C.Thus the presence of a data signal is indicated for coupling to adestination via the interface switch matrix.

In FIG. 9 a single indicia transmitter 405 is shown coupled to a singleinput line pair A of data bus 501. However, a system employing theinventive control method requires that an indicia transmitter isincluded or is associated with each possible data source. Indiciatransmitter 405 comprises a switched emitter follower Q2 which iscoupled equally into each conductor of line pair A. A transistor Q1functions as a switch coupled between the base of emitter follower Q2and ground. An indicia control signal is coupled to the base terminal oftransistor Q1 via a resistor R5. The indicia control signal may begenerated, or derived from control logic in response to a deviceoperating mode command, for example, initiation of Play mode in adigital player recorder. In an exemplary Play mode, a logical low ornominally zero volt signal is applied to resistor R5 from control logic410. The nominally zero volt signal turns off transistor Q1 which allowsthe base terminal of transistor Q2 to assume a potential ofapproximately 1.6 volts, determined by the series combination ofresistors R6, R7 and diode D1. The emitter follower action of transistorQ2 results in an emitter voltage Vs, of approximately 1 volt, which isapplied the data bus conductors via resistors R1 and R2. In non-replaymodes a logical high or nominally 5 volt signal is generated by logic410 and applied to resistor R5. The nominally 5 volt signal, coupled viaresistor R5, turns on transistor Q1 which clamps the base terminal oftransistor Q2 to ground. Thus transistor Q2 is turned off and no indiciaor sensing voltage Vs is generated.

A single indicia detector 403 is shown in FIG. 9 coupled to a bus pair Aof data bus 501. However, a system employing the inventive controlmethod requires that an indicia detector is provided for each data buspair coupled to a switch matrix. Indicia detector 403 comprises abalancing network formed by resistors R3 and R4 coupled from each busline to a parallel combination of a resistor R14 and a capacitor C2connected to ground. Resistors R11 and R12 are connected to each busline and are joined at a non-inverting input of an integrated circuitcomparator amplifier U1. An inverting input of integrated circuit U1 isconnected to a DC potential divider formed by resistors R8 and R9,coupled between +5 volts and ground and generating a voltage of about0.8 volts. When data indicia Vs is absent the data bus sits at nominallyground or zero volt potential. This nominally ground potential iscoupled via resistors R11 and R12 to the non-inverting input of IC U1.Thus with zero volts applied to the non-inverting input and 0.8 voltsapplied to the inverting input the output terminal of IC U1 assumes alow, nominally ground potential. When data indicia Vs is present thedata bus is nominally 1 volt positive relative to ground potential. The+1 volt DC indicia signal applied to the non-inverting input of IC U1causes the output terminal to assume a high, nominally supply railpotential. Thus integrated circuit U1 output signal indicates a data bussignal presence with a high level signal and a data bus signal absencewith a low level output signal.

TABLE 1 illustrates an advantageous automated interface switch apparatuscontroller associated with a digital recorder, for example, D-VHS. Therecorder mode is determined by user command, for example by manualswitch operation or IR remote control. Control logic associated with theinterface switch apparatus and digital recorder determine the userdesired mode and establish connection between the appropriate exemplaryD-VHS input or output terminal and an appropriate bus conductor.

TABLE 1 DIGITAL PLAYER/RECORDER AUTO SWITCHING MATRIX STATUS OF BUSSESA/B DIGITAL Player/Recorder MODE 0/0 0/1 1/0 RECORD WAIT B -> IN A -> INB -> A A -> B REPLAY OUT -> A OUT -> A OUT -> B OUT -> B OFF OPEN B -> AA -> B

Operation of the automated interface switch apparatus is as follows. Forexample, upon selection of a replay mode, transmitter 405 circuitry ofFIG. 8 is enabled and DC sensing voltage indicia Vs is applied to theoutput of a bus driver amplifier (not shown). Indicia detectors 401/402,associated with control logic of the automated interface switch 102,determine the presence, or absence of an indicia Vs on bus lines A or Band couple the output replay data and DC indicia voltage Vs to whichever bus line is not currently utilized i.e. has no DC sensing voltagepresent. Thus in exemplary TABLE 1, assuming the digital player/recorderis in a replay mode and bus status is 0/0, signifying no signals arepresent on either bus conductor, replay data from digitalplayer/recorder, for example D-VHS, is coupled to both conductors A andB.

If digital player/recorder 400 is controlled to assume a record mode theautomated interface switch apparatus functions as follows. The controllogic associated with the automated interface switch 102 determines thepresence or absence of a data indicia on bus line A or B, as anindicator of data signal presence. Thus in TABLE 1, bus status 1/0indicates that a data signal is present on bus A and this data signal isconnected to a recording input of the exemplary D-VHS digital recorder.Similarly, if the data signal indicia is present on bus B, the automatedcoupling connects the recording input to bus B.

An inventive aspect of the automated interface switch apparatus occurswhen a record mode is selected for the digital player/recorder but datasignals are not present on either bus A or B, i.e. bus status 0/0. Acondition such as described may occur when the transmission of thespecific program selected for recorded is delayed. Under this conditionTABLE 1 indicates a WAIT or record paused condition is applied to therecorder. The control logic associated with the automated interfaceswitch may inhibit initiation of the user selected record mode until adata signal indicia is detected on either bus conductor. Detection ofthe data indicia Vs controls coupling of data to the recording input,and in addition, may enable initiation of the pre-selected record mode.Thus, the advantageous control logic prevents the unnecessaryconsumption of recording media and ensures the desired program isrecorded without the use of a separate control bus or IR blaster.

A third exemplary audio-video-data AVD bus system is illustrated in FIG.10. FIG. 10 shows a simplified single pair daisy chained bus whichcouples between a digital recorder 400, IRD or DSS receiver 100 anddisplay 110. Advantageous automated controllers C are coupled tointerface switch apparatus 102 associated with a digital recorder 400,for example, D-VHS and interface switch apparatus 101 associated withreceiver 100 and display 110. TABLE 2 illustrates the automatedfunctions of controller C of interface switch 101 associated with anexemplary DSS™ receiver 100 and an exemplary data signal source digitalrecorder/player 400, for example, D-VHS. The receiver mode is determinedby user command, for example by manual switch operation, not shown or IRremote control. The receiver may be controlled to output data to orreceive data from the single pair bus A. Control logic associated withthe interface switch apparatus and digital recorder determine the userdesired mode and establish connection between bus conductor A and theappropriate input or output terminal of receiver 100.

TABLE 2 RECEIVER AUTO SWITCHING MATRIX STATUS OF BUS A RECEIVER MODE 0 1OUTPUT RECEIVED DATA OUT -> A OUT -> IN DATA INPUT (REPLAYED DATA) OUT-> A OUT -> A OFF OPEN OPEN

Operation of the automated interface switch apparatus is as follows. Forexample, the user determines that the receiver will receive and output aspecific program data stream. The control logic associated with theautomated interface switch 101, of receiver, 100 determines the presenceor absence of a data signal indicia, for example the DC sensing voltageVs, on bus line A. An absence of indicia on bus line A indicates thatdigital recorder/player 400 is not outputting data and consequently busline A is available for transmission of receiver 100 output data. Thereceiver output data is also coupled to the receiver decoder input fordecoding and coupling for display. When the user initiates a replaymode, controller 410 generates a play command for recorder/player 400and in addition enables generation of data indicia Vs. Indicia Vs isadded symmetrically to the replay data stream which is coupled, forexample, to the automated interface switch 102. Indicia detectors, forexample, 401/2/3/4 of FIG. 8 or 401/3 of FIG. 10 determine the absenceof an indicia Vs on, for example bus line pair A, and enable coupling ofthe data stream and indicia to bus pair A. Interface switch apparatus101 within receiver 100 detects the indicia voltage Vs and enablescoupling of the replay data for decoding by IRD 100 and display inmonitor 110. Thus the simple, single pair bus may provide automatedcoupling between two sources and a monitoring input without the use of acontrol bus conductor.

What is claimed:
 1. A signal processing apparatus for processing apacketized data stream subjected to timing perturbations, said datastream comprising a plurality of superpackets, each of said superpacketshaving a transport packet and a timestamp, said apparatus comprising:means for receiving said superpackets from said perturbed packetizeddata stream; means coupled to said receiving means for storing saidsuperpackets; means for reading respective timestamps from each of saidreceived superpackets, each said timestamp representing a time intervalbetween adjacent transport packets prior to said timing perturbations; acounter; and, means coupled to said reading means and to said counterfor generating a control signal indicating each coincidence betweensuccessive ones of said timestamps from said received superpackets and acount of said counter, said control signal initiating reading of saidsuperpackets from said storing means to restore relative timing ofadjacent transport packets existing prior to said timing perturbations.2. The apparatus of claim 1, wherein said counter is coupled to anoscillator for counting an oscillator signal generated by saidoscillator.
 3. The apparatus of claim 2, wherein said oscillator is freerunning.
 4. The apparatus of claim 2, wherein said oscillator signal iscoupled to said storing means for reading said superpackets therefrom.5. An apparatus for reproducing a recorded signal from a recordingmedium, said recorded signal being representative of a plurality ofsuperpackets, each of said plurality of superpackets having a transportpacket and a timestamp, said timestamps being indicative of timeintervals between corresponding parts of plurality of superpackets in adata stream prior to recording, said apparatus comprising: a transduceroperable with said recording medium and generating a transduced signalrepresentative of said recorded signal; means for recovering saidplurality of superpackets from said transduced signal; and, means forgenerating an output signal from said recovered plurality ofsuperpackets in which said time intervals between corresponding parts ofsaid plurality of superpackets have been restored to said time intervalsexisting prior to recording.
 6. The apparatus of claim 5, wherein saidoutput signal generating means comprises: means for storing saidrecovered plurality of superpackets; means for reading respectivetimestamps from each of said recovered plurality of superpackets; acounter; and, means coupled to said reading means and to said counterfor generating a control signal indicating synchronization betweensuccessive ones of said timestamps from said recovered plurality ofsuperpackets and a count of said counter, said control signalcontrolling reading of said plurality of superpackets from said storingmeans, said plurality of superpackets being separated by said timeintervals.
 7. An apparatus for reproducing a recorded signal from arecording medium, said recorded signal being representative of apacketized signal having a plurality of superpackets, each of saidsuperpackets having a transport packet and a timestamp, said timestampsbeing indicative of gaps between corresponding parts of saidsuperpackets in a data stream prior to recording, said apparatuscomprising: a transducer operable with said recording medium andgenerating a transduced signal representative of said recorded signal;means for recovering said plurality of superpackets from said transducedsignal; means for reading respective timestamps from each of saidrecovered superpackets; means for storing said recovered plurality ofsuperpackets; a source of a clock signal; a counter coupled to saidclock signal for counting; and, means coupled to said reading means andto said counter for generating a control signal indicating eachsynchronism between successive one of said separated timestamps and acount of said counter, said control signal initiating reading of saidsuperpackets from said storing means.
 8. The apparatus of claim 7,wherein a signal from said source is coupled to said storing means forreading said superpackets therefrom.
 9. The apparatus of claim 7,wherein said superpackets are read from said storing meansintermittently with gaps there between of variable duration.
 10. Theapparatus of claim 7, wherein said storing means is clocked by a signalfrom said source to restore said superpackets to a time sequenceexisting prior to recording on said medium.
 11. The apparatus of claim7, wherein said superpackets are read from said storing means to restoregaps between ones of said plurality of superpackets, said gaps beingsubstantially similar to gaps between said ones of said plurality ofsuperpackets established during superpacket formation.
 12. The apparatusof claim 7, wherein said source is free running.
 13. The apparatus ofclaim 7, wherein each of said superpackets has a playback rate code fordetermining a reproduction speed which differs from a speed at whichsaid recorded signal was recorded.
 14. A recording medium havingrecorded thereon an MPEG compatible signal having transport packets,wherein each transport packet is associated with a superpacket having atimestamp representing an interval between adjacent superpacketsexisting prior to recording on said medium, said timestamp beingsuitable for controlling an apparatus for reproducing said MPEGcompatible signal from said recording medium to restore said intervalsbetween said adjacent superpackets to that existing prior to recording.15. The recording medium of claim 14, wherein said timestamp controlsinitiation of reading said superpackets from said reproductionapparatus.
 16. The recording medium of claim 14, wherein said timestampcontrols initiation of reading said transport packets from saidreproduction apparatus.
 17. The recording medium of claim 14, whereinsaid timestamps control initiation of clocking by said reproductionapparatus to restore said superpackets to a time sequence existing priorto recording on said medium.
 18. The recording medium of claim 14,wherein said timestamps control said reproduction apparatus to restorean intermittent occurrence of said superpackets existing prior torecording on said medium.
 19. A recording medium having recorded thereonMPEG compatible transport packets being included in superpackets, eachof said superpackets including a timestamp and playback rate code, saidplayback rate code representing a reproducing speed for said MPEGcompatible transport packets, and being suitable for determining areproducing speed of a reproduction apparatus which differs from a speedat which said MPEG compatible transport packets were recorded.